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Complete Static Timing
Analysis Report
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SDC files support
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Performance estimation based on selected technology node and libraries
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Critical paths reports
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Generation of setup and hold report
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Embedded RTL parser and synthesis
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IEEE VHDL, Verilog and System-Verilog support
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Synthesized RTL designs optimized to Menta eFPGA architecture
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Timing or area driven
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Free from any export-control and patent issues
Place & Route
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Powerful Place & Route engine
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Low LUT usage and Optimum routing
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Timing and IO placement constraints aware
User-friendly Graphical Interface
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Manual floor planning: placement per zone or per block
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Resources usage summary within GUI or as an ASCII file
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Statistics on density
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Scriptable TCL commands
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